VHDL Simulation and Synthesis

VHDL is a hardware design-entry language which is commonly used to specify, document, simulate and implement digital electronic circuits. Whether targeting FPGAs (Field Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits) VHDL offers productivity benefits to engineers since logic circuits can be verified early in the design process and reusable design units can be easily created. This course provides participants with a fast-track route to learning VHDL and how to apply it to the design and implementation of digital circuits. The course includes a strong practical element in which attendees rapidly gain experience in VHDL coding, simulation and synthesis.

Content

VHDL background and benefits
Language syntax and constructs
Design units
Objects and data types
Modelling concurrency in VHDL
Describing hierarchy
Creating reusable design units
Simulation of VHDL designs
Synthesis and synthesisable VHDL templates
VHDL subprograms
Finite state machines
Creating test benches

Audience

The course suitable for engineers who already have a prior understanding of electronic systems and would like to be able to implement designs in VHDL code and then target an FPGA or ASIC platform. The course covers everything from the basic syntax of VHDL code to more advanced topics such as understanding how code is synthesised and performing post place and route simulations. Previous attendees to our courses have come from a wide range of industries and backgrounds such as professional audio and acoustics, digital communications, ASIC and analog electronics, and even mechanical engineering.

Event Aim

On successful completion of the course, attendees will be able to:

Be able to write synthesisable VHDL code
Be aware of the language constructs that are available
Know which features of VHDL are synthesisable and which are not
Understand how VHDL code is synthesised
Be able to create reusable VHDL design units
Understand how parallelism is represented in VHDL
Create test benches to simulate a VHDL designs
Simulate VHDL designs and analyse the simulation results
Synthesize VHDL designs for FPGAs
Perform post synthesis and post place and route VHDL simulations

Presentation

The course format is: 20% Lectures | 70% Practical Sessions | 10% Demonstrations

Laboratory Sessions: During the practical sessions, attendees shall be asked to design and verify digital circuits in VHDL and synthesise the designs for an FPGA. The designs range from simple adder circuits to more complex finite state machines, RAM models and Digital Signal Processing (DSP) components.

Course Materials: All attendees will receive electronic and printed versions of the teaching materials. A DVD containing all the simulation models used during the course will also be distributed. The notes provided form a superset of the materials presented on the course and will allow further in depth study after the course

Pre-requisites

This intense course is intended for engineers who would like to learn VHDL and use it to design and implement digital circuits. The course assumes that attendees have previous experience in digital electronic design to Bachelor level. Although not essential, attendees would also benefit from prior experience in a software programming language or a hardware description language.

Event Date

on request - Derag Hotel Prinzessin Elisabeth in Munich, Germany www.deraghotels.de

Instructor: Prof. Bob Stewart and team

Prof. Bob Stewart and team Professor Bob Stewart and his team of experienced design engineers from Steepest Ascent of have successfully presented in Europe, United States and Asia. Prof Bob Stewart has extensive experience presenting industry DSP courses in the USA and Europe. He is currently a faculty member of the Department of Electronic and Electrical Engineering at the University of Strathclyde. Prior to joining the University of Strathclyde, Prof Stewart was a visiting professor in Dept of Electrical Engineering at the University of Minnesota in 1990, and a visiting scholar at the University of Southern California in 1986/7. Since 1997 he has been a parttime visiting professor at UCLA.

Prices

1.850,00 € regular fee
1.670,00 € early registration
1.570,00 € per participant of two from the same company
1.480,00 € per participant of three or more from the same company
1.020,00 € University Rate (Please enclose evidence.)

All prices exclude German VAT

Provider

Steepest Ascent

Steepest Ascent has a long history in providing both Public and On-Site courses within the UK, USA and Europe. Through a number of European and US partners Steepest Ascent has delivered a wide range of detailed technical courses to some of the worlds top engineering and academic institutions.

www.steepestascent.com
Contact: Amreet Bhumbra
Phone: +44 141 552 8855
Email: info@steepestascent.com
Ladywell, 94 Duke Street | Glasgow, G4 0UW | United Kingdom

qaqadu event

qaqadu event gmbh offers advanced training for technical professionals.

www.qaqadu.com
Contact: Mandy Ahlendorf
Phone: +49 8151 555009 11
Email: contact@qaqadu.com
Maximilianstrasse 8 | 82319 Starnberg | Germany